With highly embedded high performance digital processors it is advantageous to provide debug facilities on-chip. Digital signal processors may operate with pipelined execution of each instruction in a sequence of instructions. Furthermore the instructions may be guarded or predicated instructions which include a prediction or guard value so that the execution of the instruction depends on resolution of the guard value. It is understood that “prediction” and “guard” have the same meaning as the term “guard” will be used hereafter. In the case of long execution pipelines using guarded instructions, the guard value may well not be resolved until the instruction is well into the pipeline and has been followed by one or more successive instructions entering the pipeline. For debugging or emulation systems problems can arise in determining which instruction or program count gave rise to a particular watched condition in the case where guarded instructions are executed in long pipelines with resolution of the guard value occurring after the instruction enters the execution pipeline.
It is an object of the present invention to provide an improved computer system and method of operating a computer system in which a debugging or watch procedure is enabled by synchronisation of two or more events even when guarded instructions are executed in an execution pipeline.